A device may be evaluated to ensure that is operates properly. For example, a processor might be tested to ensure that it receives, processes, and provides information properly. FIG. 1 is a diagram of a known functional testing system 100 in which a device under test 110 is evaluated by a functional tester 150. In particular, the functional tester 150 has a wide tester interface. That is, the function tester 150 exchanges information with the device under test 110 via all (or substantially all) of the input and output paths (e.g., pins) that comprise the device's bus 120.
There are a number of disadvantages, however, associated with a functional tester 150. For example, the bus 120 may include a large number of input and output paths. Moreover, the functional tester 150 may need to provide and/or receive information via each of the paths at the full speed of the bus 120. As a result, the design and construction of the functional tester 150 can be costly and time consuming. For example, a functional tester 150 that evaluates a processor might need to exchange information via a 300-pin bus at 533 Mega Hertz (MHz). As a result, a large number of ultra-high speed components (e.g., GaAs components) may need to be incorporated in the functional tester 150.
As another approach, FIG. 2 is a diagram of a known structural testing system 200 in which a device under test 210 is evaluated by a structural tester 250. In this case, the structural tester 250 exchanges information with the device under test 210 via a test bus 260 that includes only a subset of the paths in the bus 220. For example, a 128-pin test bus 260 might be used exchange information with a processor that has a 300-pin bus. Moreover, the structural tester 250 (e.g., a low pin count tester) may exchange information via the test bus 260 at a speed less than the full speed of the bus 220. Although the design and construction of a structural tester 250 can be less expensive and time consuming as compared to a functional tester 150, the evaluation of the device under test 210 may be less thorough. For example, because not all of the paths in the bus 220 are used, some logic paths in the device under test 210 may not be fully evaluated.
As still another approach, it is known that the structural tester 250 can use the test bus 260 to load a set of instructions into a local memory of the device under test 210 (e.g., in a cache structure). The device under test 210 then executes the instructions when the test is performed. Defining an appropriate set of instructions, however, can be difficult (e.g., because a system trace of the entire bus 220 is not easily translated into a set of appropriate instructions). Moreover, it might not be possible to evaluate some portions of the device under test 210 in this way (e.g., portions associated with input and output paths that comprise the entire bus 220).